//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2008-2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 127275
// File Date           :  2012-03-19 15:37:15 +0000 (Mon, 19 Mar 2012)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Purpose : This module contains the read mux and read pointer for the
//           read-data FIFO.
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//        *** AUTOMATICALLY GENERATED, ONLY MODIFY MARKED SECTIONS ***
//
//  Config :
//           o  FIFO Depth  = 2
//
//
//------------------------------------------------------------------------------

`include "nic400_ib_chiplink_slv_axi4_tpv_ib_defs_ysyx_rv32.v"
  
module nic400_ib_chiplink_slv_axi4_tpv_ib_w_fifo_rd_ysyx_rv32
  (
  // Outputs
  dst_valid,
  rpntr_gry_async,
  rpntr_bin,
  dst_data,

  // Inputs
  rclk,
  rresetn,
  src_data,
  wpntr_gry_async,
  dst_ready

  );

  // Read Clk, Reset and Sync Enable
  input        rclk;
  input        rresetn;

  // Write Clock Domain
  input  [1:0]  wpntr_gry_async;
  input  [72:0]    src_data;


  // Read Clock Domain
  input        dst_ready;
  output       dst_valid;
  output [1:0]  rpntr_gry_async;
  output        rpntr_bin;
  output [72:0]    dst_data;



  //------------------------------------------------------------------------
  // Registers
  //------------------------------------------------------------------------

  // read pntr registers
  reg [1:0]  rpntr_gry;
  reg        rpntr_bin;


  //------------------------------------------------------------------------
  // Wires
  //------------------------------------------------------------------------


  wire [1:0]  next_rpntr_gry;
  wire [1:0]  wpntr_gry_rsync;
  wire [1:0]  rpntr_gry_async;
  wire        next_rpntr_bin;
  wire        fifo_pop;
  wire        empty;
  wire        not_empty;

  //------------------------------------------------------------------------
  // Functions
  //------------------------------------------------------------------------

`include "nic400_ib_chiplink_slv_axi4_tpv_ib_w_fifo_fn_ysyx_rv32.v"

  //------------------------------------------------------------------------
  // Main Code
  //------------------------------------------------------------------------

  assign dst_valid = ~empty;
  assign fifo_pop = dst_ready & ~empty;
  
  assign not_empty = ~empty;

  // Synchronizer to bring the pointer into the clock domain (includes
  //   corrupt block)
  nic400_ib_chiplink_slv_axi4_tpv_ib_w_fifo_sync_ysyx_rv32 u_sync_wr_ptr_gry
  (
    .clk       (rclk),
    .resetn    (rresetn),
    .ptr_async (wpntr_gry_async),
    .ptr_sync  (wpntr_gry_rsync)
  );

  //Generate the write pointer to send cross domain  
  nic400_cdc_launch_gry_ysyx_rv32 #(2) u_cdc_launch_rd_ptr_gry
  (
    .clk       (rclk),
    .resetn    (rresetn),
    .enable    (fifo_pop),
    .in_cdc    (next_rpntr_gry),
    .out_async (rpntr_gry_async));

  // Capture the incoming data
  nic400_cdc_capt_nosync_ysyx_rv32 #(73) u_cdc_data_capt_nosync
  (
    .valid     (not_empty),
    .d_async   (src_data),
    .q         (dst_data)
  );


  // calculate next gray pointer
  assign next_rpntr_gry = nic400_ib_chiplink_slv_axi4_tpv_ib_w_fifo_next_gry_fn(rpntr_gry);

  always@(posedge rclk or negedge rresetn)
    begin : p_rpnt_seq
      if(!rresetn)
         rpntr_gry <= {2{1'b0}};
      else if(fifo_pop)
         rpntr_gry <= next_rpntr_gry;
    end


  // decode rpntr to be used to access data
   assign next_rpntr_bin = nic400_ib_chiplink_slv_axi4_tpv_ib_w_fifo_gry_to_bin_fn(next_rpntr_gry);

   // rpntr_bin is generated from register to improve data output timing
   always@(posedge rclk or negedge rresetn)
     begin : p_rpnt_bin_seq
   if(!rresetn)
      rpntr_bin  <= {1{1'b0}};
   else if(fifo_pop)
      rpntr_bin <= next_rpntr_bin;
   end

  // check if fifo is empty
  assign empty = nic400_ib_chiplink_slv_axi4_tpv_ib_w_fifo_empty_fn(wpntr_gry_rsync, rpntr_gry);



endmodule


  

`include "nic400_ib_chiplink_slv_axi4_tpv_ib_undefs_ysyx_rv32.v"

// --================================= End ===================================--
